The present invention relates generally to soldering of integrated circuits and substrates, and, more specifically, to an improved solder decal and method of forming and using.
Solder processing for standard electronic packaging applications such as integrated circuit chip interconnections routinely use evaporation or electroplating. Both of these processes are costly, and may involve many processing steps. For example, to produce a solder decal by electroplating, a metal seed layer must first be deposited on a decal substrate. Next, this seed layer is patterned to produce the desired layout, after which the plating process produces the solder structures. Finally, the patterning and unplated seed layers must be stripped away. For effective transfer, the seed layer remaining under each solder structure must not metallurgically bond to the solder during reflow. Both of these processes are also typically limited to smaller solder structures such as solder balls having a diameter of about 2-4 mils.
Other requirements such as chip rework, burn-in and test, thermally mismatched packages, and 3-D packaging usually cannot be met with solder interconnection schemes alone. For example, burn-in and test methods usually require sophisticated temporary connectors. Thermally mismatched packages require mechanically flexible connections such as copper or gold-plated pins. The cost of these temporary connectors for burn-in and test as well as substrates with tall gold-plated pins significantly increase the overall package costs.